1. Field of the Invention
The present invention relates to an inductor utilized in low noise amplifiers using RF CMOS process; and, more particularly, to an integrated inductor device for a RF transistor in low noise amplifiers using RF CMOS process.
2. Description of Related Art
Wireless portable communication devices are rapidly growing as consumers rely more on wireless communications. Consumer electronics such as cellular phones, pagers, GPS, and other wireless devices operate in a radio frequency (RF). Integrated wireless portable communications devices would allow users to utilize one device for operating in a variety of communication systems. In addition, the integration of components offers attractive savings in terms of packaging size, cost, and energy requirement.
The advance of RF CMOS technology has made it possible to integrate onto a single chip a communication operating in a certain radio frequency range which can be used in various wireless portable communications devices. An important aspect of the devices is having a low noise amplifier (LNA). The prime objective of the LNA is to produce a signal with a low noise figure and minimum power consumption.
RF low noise amplifier (hereinafter, LNA) for integrated circuit (hereinafter, IC) process generally requires RF inductors for impedance matching purposes. The impedance of the entire IC should be matched for the highest performance. The LNA usually comprises at least a RF transistor and a plurality of matching on-chip inductors and RF chokes. The plurality of inductors is for matching the impedance of the input and output of the RF transistors to obtain lowest possible noise figure and higher self-resonance frequency for wider bandwidth. However fabrication and design of on-chip inductors require a substantial amount of chip area. Usually the fabrication of an inductor on a chip requires a reserved area of the chip and other RF components will not be allowed to be designed in the substrate over an on-chip inductor reserved area. Typically, a single on-chip inductor will consume an area of about 400 microns by 400 microns. Although the design of a single inductor may not pose a large problem to the available chip area, most modest RF IC generally require at least 3 or more inductors. It should thus be appreciated that on-chip inductors used in RF IC place a very large demand on chip area besides the inherent low Q level of the inductor, which necessarily translates into larger silicon chips and greater IC chip cost.
In order to match the impedance, a RF inductance of about 5 nH is usually required. A typical RF inductor by RF silicon process can deliver the best performance with inductance of 5 nH at a frequency of 2.4 GHz, Q value less than 10, and stray capacitance greater than 7.5 xcexa9. The performance of these on-chip inductors are still very poor and LNAs usually still require an external gate matching inductor, which has much higher performance due to integration difficulty.
The most challenging component to adapt to an IC is the inductor. Inductors are an essential component in a variety of RF devices, including LNA. Inductors must be able to provide a relatively large inductance values, ideally greater than 10 nH for high performance usage while being physically small such that a compact architecture can be achieved. A problem with conventional inductors is that high inductance values (L), as required in RF chokes, require a large silicon chip area. This large area requirement prevents miniaturization of chips. In addition, physically large RF chokes cannot operate at high frequencies, where the short wavelengths necessitate physically small and high performance components. RF chokes are crucial in LNAs because they prevent RF signals from coupling back to other critical electrical circuits.
The inductance value is mainly dependent on the geometry of the inductor and its physical dimension. In fact, the inclusion of passive components will often dictate the size of system more than any other part. Thus, design of high valued inductors within compact spaces is necessary for successful RF CMOS IC.
Various methods and technologies have been developed to integrate inductors into IC processes. Attempts to integrate inductors into silicon-based circuits have yielded either inductors of low quality factor (hereinafter, Q value) and high loss, as a result high noise figure and stray capacitance.
In silicon based RF CMOS process, RF inductors are generally achieved by thin metal wires and therefore suffer high stray capacitance and low self-resonance frequency due to the encasing of the transmission line conductors in the oxide insulators. The thickness of the thin metal wires are usually less than 1 um for logic process and approximately 2 um for the top metal layer of special RF process. A method of improving the performance of the inductor is to increase the width of the conductive paths. Because the conductive path is spiral-shaped, magnetic fields induced by current flow tend to force the current to flow along the inner or shorter edges of the spiral conductive path. Because of these xe2x80x9cedge effectsxe2x80x9d, increasing the width beyond a particular point ceases to show a concomitant improvement on the performance.
FIG. 1 shows a schematic diagram of a conventional LNA for RF CMOS process. The conventional LNA has at least a RF transistor 10, which its control terminal, input terminal, and output terminal are individually coupled to a separate inductor for impedance matching purposes. Matching inductor 11 is coupled to the gate of RF transistor 10 for matching the impedance of the RF input signal. A gate bias voltage supply is also connected to the gate of RF transistor 10 via a RF choke 15 for supply modulation and to ground via a bypass capacitor 17. Matching inductor 12 is coupled to the drain of RF transistor 10 for matching the impedance of the RF output signal. A drain bias voltage supply is also connected to the drain of RF transistor 10 via a RF choke 14 for supply modulation and to ground via a bypass capacitor 16. Matching inductor 13 is coupled to the source of the RF transistor 10 and ground.
The input, output, and control RF signals are individually coupled to separate inductors for impedance matching. At least 2 inductors are needed for one RF transistors and a LNA usually requires 2 to 4 inductors. Since on-chip inductors are usually low in Q value and require a substantial amount of area, the present invention provides an innovation integrated inductor device for use in IC systems which have superior quality factors, low noise figures, and substantially decreased size required for the inductors, all being obtained at a zero added fabrication.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
According to the above mentioned problems, one object of the present invention is to provide an integrated inductor device for a RF transistor, which has a high Q value, low stray capacitance, and a reduced area, which can be manufactured using conventional RF CMOS techniques at a lower cost. Furthermore the present invention relates to a problem of providing a RF CMOS IC integrated inductor device with higher performance for a wide range of frequencies.
The present invention provides a RF transistor with an integrated inductor device for the gate, drain, and source of the RF transistor. The integrated inductor device formed in the shape of a square-loop is collocated in the same defined area and space. Wherein the integrated inductor device is formed by a plurality of metal runners connected at preferably 90 degrees for forming three conductive paths in a square spiral shape while staying geometrically parallel to each other. The adjacent conductive paths carry a current in the same direction and each conductive path generates a magnetic field. The conductive paths are disposed such that the combined magnetic filed generated by the conductive paths in a space between the conductive paths is greater than the magnetic field generated by each of the conductive path in that space alone. All three conductive paths give positive contribution to a total magnetic flux. Lenz""s law states (1):
Lgate digate/dt=Nturnd(xcfx86gate+xcfx86drain+xcfx86source)/dt
where, Lgate is the inductance (L) value for the gate for example;
igate is the current passed through the conductive path that is connected to for example the gate;
Nturn is the total number of turns of the integrated inductor device;
xcfx86gate, xcfx86drain, xcfx86source are the magnetic flux of the gate, drain, and source respectively.
According to Lenz""s law, inductance (L) is directly proportional to the number of turns of an inductor and the total magnetic flux. Therefore, the increased magnetic flux indicates a decrease in the number of turns of the integrated inductor device for a given level of inductance (L). Because fewer turns are used within a device formed in accordance with the present invention, the stray capacitance in the inductor device will be lower. Moreover because less metal runners are required for the inductor device, the series resistance of the inductor device is also reduced. Therefore advantageously, this design also has the surprising effect of providing a high inductance (L) value. The equation that renders the relationship between the quality factor (Q), inductance (L) value, and series resistance (R) is equation (2):
Q=.omega..sub.0 L/R
where, .omega..sub.0 is the resonant angular frequency of oscillation;
L is the inductance of the coil; and
R is the series resistance taking into account the losses. By the equation, a much higher Q value is realized as a combined effect of a reduced series resistance (R) value and a higher inductance (L) value. As a result of the improvement of the integrated inductor device, the LNA also has a lower signal-to-noise (S/N) ratio and requires less overall chip area.